1. Field of the Invention
This invention is generally related to a method for interconnecting integrated circuits with high volumetric efficiency and, more particularly, to a method of applying edge metallization for use in a three-dimensional module.
2. Description of the Related Art
Interconnecting high performance circuits, such as very large scale integrated circuit (VLSI) chips, presents the circuit designer with several problems. VLSI chips often have one hundred or more pins, each with a pitch of less than ten mils. That is to say, the sum of the conductor line width plus the distance between two adjacent lines is less than ten thousandths of an inch. The VLSI chips typically must be joined to a printed circuit board which has a pitch of twenty-five to fifty mils. In order to connect a VLSI chip to the circuit board, a "fan out" region of interconnecting lines must be provided. The fan out region occupies valuable space on the circuit board, and the long lead lengths contribute high inductance. Thus, the fan out design limits the high speed capability of the circuit. In multi-chip substrates, which are comprised of numerous chips mounted on the same substrate, interconnections among chips on the substrate allow high speed performance, but substantial performance loss occurs in going from the substrate to the printed circuit board. Not only is soldering several hundred pins on twenty-five mil centers a very difficult task, but in addition, thermal mismatches and hermeticity requirements affect the size of substrate which can be created practically. According to Rent's rule, the number of pins required increases in accordance with the square root of the number of gates enclosed by the circuitry. Since each pin must be hermetically sealed, the advantage of multi-chip substrates is severely limited by the unavailability of hermetic packages which can seal more than about three hundred pins.
A method of selectively interconnecting the edge contact areas of a plurality of tightly stacked substrates having integrated circuit patterns thereon is described in commonly assigned U.S. Pat. No. 5,019,946, issued May 28, 1991, which is herein incorporated by reference. Fabrication of high density interconnect (HDI) circuits for three-dimensional module formation requires the I/O (i.e., input/output) metal fingers (i.e., metallization exposed to areas outside the integrated circuit) to be extended over the edges of the substrate. Extending titanium/aluminum I/O metal fingers over the substrate edges during I/O metal patterning prior to circuit fabrication is difficult since these are sputter deposited films and thickness conformity over an edge is forty percent at best. Even if it were possible to reliably use Ti/Al, it would be difficult to protect the metal during subsequent processing because the I/O metal on the substrate edge, unlike the I/O metal on the top, is exposed. As a result, aluminum and titanium would be exposed to all wet chemical treatments normally seen during circuit fabrication. These metals are not compatible with many chemicals and would be etched away.
The use of alternate metals compatible with the wet chemical process, such as chromium/gold or TiW/gold is feasible if the gold layer is electroplated to obtain good step coverage over the edge. These metal combinations, however, are not desirable for applications in which the circuit is exposed to x-rays. Chromium/copper lines capped with electrolessly plated nickel and thinner gold might also be feasible, but the nickel and gold layers must be pinhole free. Any exposed edge metal would require isolation during sputtering steps. Additionally, current conduction from the topside metal through the vias and I/O metal fingers may cause via damage and/or copper plating on the fingers and substrate backside, shorting them together.
Finally, any scheme which places the I/O metal over the substrate edges at the beginning of the process would suffer from the possibility of being mechanically damaged during subsequent processing. Cleaning residual polymers off of the metallized substrate edges after many spray and spin coating steps during the entire process is also not trivial.